MRAM is a non-volatile computer memory technology based on magnetoresistance. One type of MRAM cell is a spin torque transfer MRAM (STT-MRAM) cell, which includes a magnetic cell core supported by a substrate. As shown in FIG. 1, a known STT-MRAM cell 10 generally includes at least two magnetic regions, for example, a “fixed region” 12 (also known in the art as a “pinned region”) and a “free region” 14, with a non-magnetic region 16 between the fixed region 12 and the free region 14. The fixed region 12, free region 14, and non-magnetic region 16 form a magnetic tunnel junction region (MTJ) of the STT-MRAM cell 10. The STT-MRAM cell 10 may also include a first electrode 18 operably coupled to the fixed region 12 and a second electrode 20 operably coupled to the free region 14. The fixed region 12 and the free region 14 may exhibit magnetic orientations that are either horizontally oriented (“in-plane”) as shown in FIG. 1 by arrows, or perpendicularly oriented (“out-of-plane”) relative to the width of the regions. The fixed region 12 includes a magnetic material that has a substantially fixed magnetic orientation (e.g., a non-switchable magnetic orientation during normal operation). The free region 14, on the other hand, includes a magnetic material that has a magnetic orientation that may be switched, during operation of the cell, between a “parallel” configuration and an “anti-parallel” configuration. In the parallel configuration, the magnetic orientations of the fixed region and the free region are directed in the same direction (e.g., north and north, east and east, south and south, or west and west, respectively). In the “anti-parallel” configuration, the magnetic orientations of the fixed region 12 and the free region 14 are directed in opposite directions (e.g., north and south, east and west, south and north, or west and east, respectively). In the parallel configuration, the STT-MRAM cell 10 exhibits a lower electrical resistance across the magnetoresistive elements (e.g., the fixed region 12 and free region 14). This state of low electrical resistance may be defined as a “0” logic state of the STT-MRAM cell 10. In the anti-parallel configuration, the STT-MRAM cell 10 exhibits a higher electrical resistance across the magnetoresistive elements. This state of high electrical resistance may be defined as a “1” logic state of the STT-MRAM cell 10.
Switching of the magnetic orientation of the free region 14 may be accomplished by passing a programming current through the STT-MRAM cell 10 and the fixed region 12 and free region 14 therein. The fixed region 12 polarizes the electron spin of the programming current, and torque is created as the spin-polarized current passes through the cell 10. The spin-polarized electron current exerts torque on the free region 14. When the torque of the spin-polarized electron current passing through the cell 10 is greater than a critical switching current density (Jc) of the free region 14, the direction of the magnetic orientation of the free region 14 is switched. Thus, the programming current can be used to alter the electrical resistance across the magnetic fixed and free regions 12, 14. The resulting high or low electrical resistance states across the magnetoresistive elements enable the read and write operations of the STT-MRAM cell. After switching the magnetic orientation of the free region 14 to achieve the parallel configuration or the anti-parallel configuration associated with a desired logic state, the magnetic orientation of the free region 14 is usually desired to be maintained, during a “storage” stage, until the STT-MRAM cell 10 is to be rewritten to a different configuration (i.e., to a different logic state). Accordingly, the STT-MRAM cell 10 is non-volatile and holds its logic state even in the absence of applied power.
High density cell array layouts are desired to obtain STT-MRAM devices with high data storage capabilities. However, STT-MRAM conventionally requires higher current to read and/or write logic states compared to other non-volatile memory, such as NAND Flash memory. Several publications describe efforts to achieve high density cell array layout and/or to reduce the current required to read and/or write logic states in STT-MRAM devices. For example, U.S. Patent Application Publication No. 2007/0279963 to Kenji Tsuchida et al., filed Feb. 9, 2007, titled “Semiconductor Memory” (hereinafter “the '963 Publication”) describes an STT-MRAM cell layout with a dual-access trench. The '963 Publication describes a conventional layout that achieves a cell size of 12F2, where F is a smallest feature size (e.g., width of a line, trench, or other feature). The '963 Publication describes staggering the cells to achieve a smaller 8F2 cell size. The article by Bo Zhao et al. titled “Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices,” published in the Proceedings of the Design, Automation & Test in Europe Conference & Exhibition held Mar. 12-16, 2012 (hereinafter “Zhao”), describes a source line that is parallel to a word line direction and that is used as a source for all cells along the source line. Zhao also describes a cell arrangement to achieve a 6F2 cell size.